This invention relates to semiconductor memory devices with redundancy circuits, and more particularly to an improvement of programmable spare decoders in semiconductor memory devices.
In recent years, in semiconductor devices of a very high degree of integration, called "VLSI" (very large scale integration), with increase of integration density, the miniaturization of elements and the size increase of chips have been amazing. For this reason, the probability of a defective bit occurring in a semiconductor chip has become greater and a reduction of the manufacturing yield has occurred. In order to solve this problem, auxiliary decoders and spare bits are formed in the chip. Semiconductor integrated circuit devices have been developed in which, is defective bit, it is replaced with a spare bit by means of an auxiliary decoder. These circuits are called "redundancy circuits." In order to replace the defective bit with a spare bit, the auxiliary decoder can be programmed so that the defective bit is disconnected from the device by a programmable fuse element, and the spare bit selected.
FIG. 1 shows a buffer circuit, a main decoder circuit and a programmable spare decoder circuit in a MOS (metal oxide semiconductor) dynamic RAM (random access memory). Address buffers 11.sub.0, 11.sub.1, 11.sub.2, 11.sub.3 are provided to receive address inputs Ai, Aj, Ak and Al. Each of the address buffers 11.sub.0 to 11.sub.3 outputs two signals, one in phase with its input signal, and the other out of phase, i.e. a complementary signal. Main decoders are composed of NOR circuits 12.sub.0 to 12.sub.15, which receive different combinations of two signals output from buffers 11.sub.0 to 11.sub.3.
One of the decoders 12.sub.0 to 12.sub.15 is energized according to the logic of the address input, and the energized decoder energizes that one of the bit lines B.sub.0 to B.sub.15 which is connected to the energized decoder. For example, if a defective bit is detected in the bit line B.sub.0 connected to decoder 12.sub.0 according to a known method, fuse 13.sub.0 between decoder 12.sub.0 and bit line B.sub.0 is opened or burned according to a relevant known method to disconnect decoder 12.sub.0 from the memory. The spare decoder 10 is comprised of fuses 15.sub.0 to 15.sub.7 coupled with all outputs Ai, Ai to Al, Al of address buffers 11.sub.0 to 11.sub.3 and a NOR circuit 14 coupled with those fuses. Spare decoder 10 designates an auxiliary or spare bit to repair the defective bit. To designate the auxiliary bit, it is necessary to program spare decoder 10 so that the logic of the spare decoder 10 will be equal to that of the main decoder connected to the defective bit. This can be attained by selectively opening fuses 15.sub.0 to 15.sub.7 so as to have the same program. In this case, the number of fuses to be opened is the half of the buffer outputs Ai, Ai to Al, Al.
In recent years, a laser has been used for opening or burning these fuse elements. When a laser is used, the accuracy of the opening operation is relatively improved, but is still insufficient. The number of opening errors increases as the number of fuses to be opened increases. Therefore, a decrease in the number of burned fuses leads to improvement of repairing accuracy of defective elements.
The main decoders 12.sub.0 to 12.sub.15 used in the conventional MOS dynamic RAM are constructed with NOR circuits. In all of these NOR circuits, in a precharge mode, their output nodes are precharged to logical high level. In an active mode, nodes other than a selected node are discharged to logical low level. The discharge of the non-select nodes consumes much power. Reduction of the power dissipation is a strong demand in this field.